The present invention relates to a mantissa processing circuit for executing the addition and subtraction of mantissa parts of two operands and for performing rounding and normalization for the result of addition and subtraction of the mantissa parts in a floating point arithmetic apparatus for addition and subtraction which receives two floating point numbers as the operands, each floating point number having a sign bit, an exponent part and the mantissa part and being normalized.
In the field of scientific and technical calculation, a floating point number has mainly been used as the expression form of a real number in a computer because precision in calculation is high, a wide numerical range can be expressed, and the like.
By way of example, the format of a 64-bit normalized double-precision floating point number provided by IEEE754 is shown in FIG. 5. In FIG. 5, S denotes a sign bit of 1 bit, e denotes an exponent part of 11 bits, and m is a mantissa part of 52 bits from the most significant bit M to the least significant bit L. A real number expressed by the floating point number of the above-mentioned format is as follows. EQU (-1).sup.S 2.sup.e-1023 (1. m)
More specifically, there is adopted the normalized expression form in which the value of the exponent part e is adjusted such that a virtual non-zero value bit and a fracture point are positioned in the higher order than the most significant bit M of the mantissa part m.
FIG. 6 is a format diagram showing a method for treating the mantissa (fraction) part m for addition and subtraction in the floating point arithmetic apparatus. The sign bit S shown in FIG. 5, and an extended bit u and a leading bit v forming an integer part of 2 bits are sequentially added to the higher order than the most significant bit M of the mantissa part m of n bits (hereinafter, the number of bits of the mantissa part m is represented by n). A value of 01 is set to the integer part uv formed by the extended bit u and the leading bit v (u=0, v=1). A guard bit g and a round bit r are sequentially added to the lower order than the least significant bit L of the mantissa part m. A value of 00 is set to the guard bit g and the round bit r (g=r=0). There are some cases where a sticky bit s for expressing the presence of a bit-discard is added to the lower order than the round bit r. In this case, however, there is no sticky bit s. More specifically, the mantissa part m is treated as mantissa data having the following data structure of (n+5) bits in the floating point arithmetic apparatus. ##EQU1##
In the case where two operands are the above-mentioned normalized floating point numbers, addition and subtraction are executed in accordance with the following steps (1) to (7), for example.
(1) The values of the exponent parts of the operands are compared with each other.
(2) In the case where the values of the exponent parts do not correspond to each other, the mantissa data of one of the operands which has the smaller exponent part than that of the other is shifted by a bit number equal to the difference between the values of the exponent parts in the low order direction, i.e., to the right. Consequently, the mantissa data of the operands are aligned in bits. This operation is called "preshift". When executing preshift, the non-zero value of the leading bit v enters the fraction part, and the value of the least significant bit L of the fraction part sequentially goes out to the guard bit g and the round bit r.
(3) Binary addition and subtraction are executed on two mantissa data so as to obtain a first intermediate result (intermediate sum). In this case, there is executed the binary addition and subtraction on (n+5) bits including the sign bit S, extended bit u, leading bit v, guard bit g and round bit r. In case of subtraction, all the values of (n+5) bits of the mantissa data as a subtrahend are inverted. The values thus inverted are binary-added to the mantissa data as a minuend. Then, 1 is added to the round bit r of the result of the binary addition. In other words, 2's complement of the subtrahend is added to the minuend.
(4) To set significant bits to n bits, 1 is added to a bit of the first intermediate result so as to obtain a second intermediate result (rounding result). A bit as a target of rounding addition is chosen among the least significant bit L, the guard bit g and the round bit r is consideration of normalization.
By way of example, when a first intermediate result R1 is as follows, 1 is added to the least significant bit L of the fraction part so as to set to the significant bits n bits of the leading bit v and succeeding bits which are subsequent to the extended bit u of the non-zero value. ##EQU2##
When the first intermediate result R1 is negative as follows, the values of (n+4) bits other than the sign bit S of the first intermediate result R1 are inverted in order to execute rounding and positive-numbering of the mantissa part. Then, 1 is added to the round bit r so that the second intermediate result is obtained. ##EQU3##
When the first intermediate result R1 is as follows, the round bit r is included in the significant bits of n bits. Consequently, rounding addition is not executed. ##EQU4##
(5) The direction and quantity of postshift to be applied to the second intermediate result for normalization are determined, which is called postshift-count-encoding. By way of example, when a second intermediate result R2 is as follows, it is necessary to shift the second intermediate result R2 by 1 bit to the right for normalization. ##EQU5##
When the second intermediate result R2 is as follows, it is necessary to shift the second intermediate result R2 by 2 bits to the left for normalization. ##EQU6##
Consequently, in the case where the value of the integer part uv is 00, the number k of zero value bits is examined from the leading bit v to the first non-zero value bit of the second intermediate result R2 sequentially in the low order direction. The number k of the zero value bits is a left postshift quantity. When the value of the extended bit u of the integer bit uv is 1, k=-1 (postshift is executed by 1 bit to the right). When the value of the integer part uv is 01, k=0 (postshift is not executed).
(6) The second intermediate result R2 is actually shifted to the right or left in accordance with the shift quantity k obtained in (5) (a postshift quantity based on the second intermediate result R2). As the mantissa part of a calculation result fetched n bits from the most significant bit M to the least significant bit L of the fraction part of the mantissa data after postshift. The sign bit S of the mantissa data after postshift is fetched. The sign bit S thus fetched is the sign bit of the calculation result.
(7) Correspondingly to the postshift of the second intermediate result R2 by the shift quantity k, the postshift quantity k (=-1, 0, +1, +2, . . . ) is subtracted from the value of the greater exponent part of two operands. A value thus obtained is the exponent part of the calculation result.
According to the steps (1) to (7), there can be obtained the calculation result comprising a normalized format shown in FIG. 5 which has a mantissa part as the result of rounding addition.
FIG. 4 is a block diagram showing an example of a mantissa processing circuit for executing the steps (3) to (6) in a conventional floating point arithmetic apparatus for executing the addition and subtraction of normalized floating point numbers in accordance with the steps (1) to (7). In FIG. 4, the reference numeral 41 denotes an arithmetic unit, the reference numeral 42 denotes a rounding adder, the reference numeral 43 denotes a postshift-count-encode circuit (PSCE circuit), and the reference numeral 44 denotes a postshift circuit. The arithmetic unit 41 serves to execute the binary addition and subtraction of mantissa data ma and mb to which preshift has been already applied, and to output a result as a first intermediate result (intermediate sum) R1. The rounding adder 42 serves to execute addition for rounding and positive-numbering the first intermediate result R1 from the arithmetic unit 41, and to output a result as a second intermediate result (rounding result) R2. The PSCE circuit 43 serves to determine a postshift quantity k (=-1, 0, +1, +2, . . . ) to be applied to the second intermediate result R2 from the rounding adder 42 for normalization based on the second intermediate result R2. The postshift circuit 44 serves to actually shift the second intermediate result R2 from the rounding adder 42 to the right or left in accordance with the shift quantity k from the PSCE circuit 43, and to output the result of postshift as the mantissa data mc of a calculation result.
The mantissa processing circuit of the conventional floating point arithmetic apparatus for addition and subtraction has a structure in which the processing for the first intermediate result (intermediate sum) R1 executed by the rounding adder 42 is terminated, and postshift-count-encoding is then executed by the PSCE circuit 43 based on the second intermediate result (rounding result) R2 outputted from the rounding adder 42. Consequently, the above-mentioned structure is the bottleneck of high speed calculation.
It is an object of the present invention to improve a mantissa processing circuit for executing the addition and subtraction of mantissa parts of two operands and for performing rounding and normalization for the result of addition and subtraction so that the high speed execution of addition and subtraction can be realized in a floating point arithmetic apparatus.